CROSS-LAYER HW–SW CO-VERIFICATION USING C-TEST INTEGRATION IN UVM ENVIRONMENTS

Abstract

Contemporary SoCs require the addition of comprehensive cross-layer verification to integrate hardware and embedded software test cases to discover bugs in the hardware-software integration that can not be identified by live tests in either domain. Traditional verification processes tend to break RTL functional verification and embedded software validation into independent processes causing blind spots to surface late in the silicon lifecycle. The following paper describes a simple way of including C-based software tests into UVM-based hardware testbenches to provide unified stimulus generation, better coverage closure and more realistic corner-case verification. We outline the infrastructure needed, the way promising virtual registers are designed, and how the means of synchronization with their help are achieved so as to enable coherent HW-Software co-verification. The measures in coverage and bug detection are shown by a real-world case study of an AXI-based SoC. They provide lessons learned and best practices in order to facilitate the adoption of this methodology at scale by the design teams.