LOW-POWER AND HIGH SPEED 8-BIT WALLACE TREE + MODIFIED BOOTH MULTIPLIER WITH POWER GATING & PIPELINING FOR IOT/EDGE

Abstract

The rapid evolution of edge computing and the widespread adoption of Internet of Things (IoT) devices have created an urgent demand for arithmetic units that deliver both high performance and low power consumption. Multipliers, as fundamental components in digital signal processing (DSP), machine learning, and cryptographic systems, are often the primary bottleneck in terms of speed, area, and energy efficiency. This paper introduces a novel multiplier architecture that combines Modified Booth Encoding (MBE), Wallace Tree compression, and a Carry Lookahead Adder (CLA) to achieve significant improvements in power, area, and delay. The design further incorporates pipelining to enhance throughput and integrates power gating to minimize leakage, making it highly suitable for energy-constrained environments. The architecture is implemented in Verilog HDL, functionally verified using ModelSim, and analyzed with open-source tools such as GTKWave and matplotlib. Synthesis and simulation results for both 8-bit and 16-bit implementations demonstrate up to 59% reduction in power, 48% area savings, and a 70% improvement in power-delay product (PDP) compared to conventional Array and Booth+CSA multipliers. These findings validate the proposed design’s applicability for next-generation edge and IoT platforms, where energy efficiency and compact area are critical.