AUTOMATED SEQUENCE ITEM GENERATION FOR DIFFERENT SERIAL COMMUNICATION PROTOCOLS

Abstract

            Due to the complexity of Application Specific Integrated Circuits , the efforts required for designing and verifying are increasing at higher rate. Researches are mostly conducted to reduce the design time. Verification environment generates and drives the signals to design under test  based on the respective frame format for every specific protocol. The coding process is done manually, which consumes more time. To overcome this, an automated script has been proposed to reduce the verification time. The frame format of a protocol which needs to be verified is fed into the spreadsheet, results in generation of sequence item. Thus, resulting in 75% reduction of time while coding the sequence item.