A RECONFIGURABLE HARDWARE ARCHITECTURE OF AHB PROTOCOL USING MACHINE LEARNING TECHNIQUE IN ASIC AND FPGA

Abstract

In modern ASIC and FPGA systems,
integrating Machine Learning (ML)
techniques is essential for achieving high
accuracy, speed, and power efficiency in
applications such as large-scale data
processing and automotive systems. This
work presents a versatile hardware
architecture that combines an MLdriven Support Vector Machine (SVM)
with a high-speed AHB protocol and
Floating Point (FP) operations. Efficient
communication is enabled through I2C
and I2S interfaces, while an AHB-toAPB bridge ensures seamless
connectivity between the Fabric
Reconfigurable Multi-Processor
(FDPM) and its peripherals.
To enhance system security, the design
integrates SHA-256 and AES algorithms,
and Double-Precision Floating Point
(DPFP) arithmetic operations are
employed to improve ML computation
accuracy. The architecture, developed in
Verilog HDL, undergoes verification
using LINT and Spyglass CDC tools.
ASIC synthesis is performed using the
DC Compiler, and FPGA
implementation utilizes Vivado Design
Suite 2018.1, validated on a Zynq
processor via the SDK tool.
Experimental results show an 18%
increase in throughput, a 21% power
reduction, and a 34% latency decrease,
demonstrating the design’s efficiency for
ML-based hardware applications.