DESIGN AND IMPLEMENTATION OF ENERGY EFFICIENT ARITHMETIC AND LOGIC UNIT USING 45 NM TECHNOLOGY BASED ON HYBRID LOGIC ADDER

Abstract

The Arithmetic and Logic Unit (ALU) is a fundamental block of any digital processor, responsible for executing arithmetic and logical operations as its name suggests. In modern processors, ALUs are required to perform numerous mathematical operations rapidly on specific datasets. Therefore, improving operational speed while minimizing power usage directly enhances the overall throughput of the digital system. To achieve this, the ALU requires an adder circuit that offers high speed, low power consumption, and efficient performance.This work focuses on designing and implementing a compact, energy-efficient one-bit full adder by integrating Pass Transistor Logic (PTL) with the Transmission Gate technique. The adder design is optimized in terms of geometry to achieve better performance across power, area, and delay metrics. The proposed one-bit full adder cell exhibits desirable features such as low power dissipation and a reduced number of transistors. The architecture is implemented using 45 nm CMOS technology in the Micro Wind 3.9 environment. Furthermore, the proposed hybrid 1-bit adder design is scalable to a 16-bit ALU configuration while maintaining low power operation. The complete adder and ALU system function at a supply voltage of 1.2 V. Compared to conventional 17T and FA-11T designs, the proposed hybrid adder achieves approximately 30% reduction in power consumption.